Magnetic flux trapping degrades the performance and in extreme cases makes superconducting digital circuits completely nonoperational. This parasitic effect can be partly kept under control by a reduction of the residual field. However, the best known protection tool is cutting long narrow openings (moats) in wide superconductor thin films. It is supposed that the undesirable residual magnetic field is frozen in the dedicated moats instead of being frozen in vortices randomly distributed along the film. In other words, the moats serve as landfills, i.e. they immobilize vortices by converting them into quantized fluxes frozen in the moats. So far intuition plays a more significant role than science in the selection of geometry and density of the moats. We have developed a rigorous procedure for calculation of Gibbs potentials for arbitrary shaped films exposed by magnetic fields. In particular, this procedure allows the potentials with and without vortices and/or fluxes frozen in moats to be compared. We numerically simulated evolutions of Gibbs potentials of slowly cooled films exposed to constant residual magnetic field. The real distribution of vortices and fluxes trapped in the moats should correspond to those with the lowest Gibbs potential. The superconductor film is immune to the trapping of Pearl vortices if the lowest Gibbs potential is achieved without such vortices. Vice versa, if the lowest Gibbs potential results in a flux pattern with trapped vortices, we know that the geometry and density of moats at the given residual magnetic field are not suitable for microelectronics application. We also discuss how to convert the proposed approach into a routine CAD procedure.

Timing variability of active devices, such as logic cells consisting of Josephson junctions, and that of passive transmission lines (PTLs) are different in SFQ digital circuits. For designing a timing-variability-aware SFQ layout, length of PTLs from the clock-source to input terminals should be the same for each gate in the layout. It is difficult to manage length of PTLs manually, and to obtain a compact layout systematically. In this paper, a new automatic wire-routing method for digital SFQ circuits using PTL wiring is proposed. The routing method can generate PTL wiring with matched length for each gate.
In the proposed method, PTL wiring between adjacent logic-gate islands is considered in a similar way as channel routing of CMOS layout designs. Because PTL is used, each connection is point-to-point. The method generates wiring considering minimization of wiring area between islands. The generated wiring consists of two regions: minimum-length wiring area and length matching area. In the minimum-length wiring area, each connection is realized by wiring with Manhattan distance. In the length matching area, zigzag wiring is generated to match the total wire-length for input terminals. This problem is formulated as an instance of integer linear programming (ILP) by representing dependencies of wiring location for connections as formulas. ILP problem is the problem to find a set of integer values for minimizing (or maximizing) a linear objective function under linear constraints. Instances of ILP can be solved by ILP solvers.
The proposed method was implemented as a design tool and evaluated by generating wiring. Instances of ILP were obtained with the design tool, and solved by an ILP solver (IBM CPLEX 12.6.0.0) on Intel Xeon E5-1620 processor. Evaluation results show that wiring of a 4-bit Sklansky adder is done with 19.7 seconds and total layout area of the adder is 2.82 mm² using the cell library developed with AIST advanced process (ADP2).

This work has been supported in part by ALCA JST. This work has been supported in part by VLSI Design and Education Center (VDEC), the University of Tokyo with the collaboration with Cadence Corporation.

It has been shown that superconductive integrated circuit layouts can be modelled for current distribution calculations and inductance extraction with the rectangular segments used by the popular FastHenry numerical solver. These rectangular segments connect nodes; the placement of which allows true-to-geometry representation of height effects in non-planarized processes. However, the uni-axial nature of these segments have always created meshing inefficiencies where two or three-dimensional current flow, non-Manhattan layouts, via structures or ground planes with many moats need to be modelled. We show how the tetrahedral volume elements of a new solver, TetraHenry, are used to model layouts in modern multi-layer planarized processes. We discuss the modelling assumptions used to integrate tetrahedral meshes into InductEx, show advantages and disadvantages compared to FastHenry’s rectangular segments, and compare accuracy. We also discuss why tetrahedral meshing is much more efficient than rectangular segments for large models, and show the full-chip extraction possibilities opened up by this new method for inductance extraction and bias current distribution calculations in superconducting integrated circuits.

This work was supported in part by the South African National Research Foundation, grant number 93586.

In July 2014 we synthesized the first quantum-accurate sine waves having a root-mean-square (rms) output voltage of 1 V [1]. This synthesizer used a single chip with four arrays of Josephson junctions which were operated in their second quantized voltage state, where each junction generates precisely two pulses for every input bias pulse. The quantum accuracy of this waveform was maintained over a current offset range of 0.4 mA. We recently increased the range of quantum-accurate 1 V rms performance to 2.1 mA, a five-fold improvement, using a new chip with twice as many junctions which are operated in their first quantized voltage state [2]. The increased number of junctions is possible because of advances in the microwave circuit design that improve the uniformity of the input bias pulse across the junction array. We describe the circuit improvements and device operation, and we demonstrate the system capabilities by showing measured spectra of perfectly quantized 1 Hz and 2 kHz sine waves. We also present additional circuit and system enhancements that improve the synthesizer performance at frequencies between 20 kHz and 1 MHz.
[1] S. P. Benz, S. B. Waltman, A. E. Fox, P. D. Dresselhaus, A. Rüfenacht, J. M. Underwood, L. A. Howe, R. E. Schwall and C. J. Burroughs, “One-Volt Josephson Arbitrary Waveform Synthesizer,” IEEE Trans. Appl. Supercond., vol. 25, no. 1, pp. 1300108, Feb. 2014.
[2] S. P. Benz, S. B. Waltman, A. E. Fox, P. D. Dresselhaus, A. Rüfenacht, L. A. Howe, R. E. Schwall and N. E. Flowers-Jacobs, “Performance Improvements for the NIST 1 V Josephson Arbitrary Waveform Synthesizer,” IEEE Trans. Appl. Supercond., vol. 25, no. 3, pp. 1400105, June 2015.

Novel computing devices bring forth the need to re-evaluate and potentially develop new systematic methodologies that enable their large-scale integration of complex circuits and systems. Adiabatic quantum-flux-parametron (AQFP) logic is an emerging technology in superconducting electronics that shows promise towards building extremely energy efficient computing systems with bit energies approaching 100k_BT and has already demonstrated circuits consisting of more than 1000 Josephson junctions. AQFP logic circuits are driven by an AC power-clock bias and at low complexities, it is not completely necessary to consider the distribution of the power-clock lines and how it effects the timing (and thus the operation) of the logic circuits. However, the lengthy distribution of the clock lines in VLSI AQFP circuits will certainly create a significant amount of clock skew between logical elements that must be accounted for throughout the entire design process. In this paper, we provide a comprehensive study on the timing implications of AQFP circuits through simulation. We clearly define what is the timing window that data should arrive for AQFP gates with respect to its clock phase and how this timing window is dependent on the clock frequency as well as the clocking implementation (e.g. 3-phase, 4-phase, and resonant clocking). Additionally, we investigate higher-order timing effects such as the influence of the data input arrival, within the timing window, on the output propagation delay. Lastly, we analyze the state-dependent energy dissipation of AQFP logic gates and its compounding effect on the overall power consumption of high-complexity VLSI circuits (~50k Josephson junctions). Such an approach will provide invaluable timing and switching energy data for EDA tools and Verilog models developed for logic-level simulation of more complex VLSI AQFP circuits to ensure timing closure of critical feedback loops and estimate data-dependent energy dissipation.

This work was supported by a Grant-in-Aid for Scientific Research (S) (No. 26220904) from the Japan Society for the Promotion of Science (JSPS).

We present experimental results of Johnson noise thermometry (JNT) with a quantum voltage noise source (QVNS) based on rapid single flux quantum technology. QVNS is used as a noise power reference in a JNT system for the measurement of the Boltzmann constant k toward the redefinition of the SI.
We used integrated QVNS (IQVNS) consisting of a pseudo-random number generator (PRNG), variable pulse number multiplier (VPNM) and a voltage multiplier (VM) on a 5 mm x 5 mm chip. By sending unmodulated clock signal to IQVNS chip we can obtain quantum-accurate and calculable noise waveforms necessary for the precise determination of Boltzmann constant using the Johnson-Nyquist formula.
In contrast to a QVNS based on a pulse-driven Josephson junction (JJ) arrays driven by a commercial pulse pattern generator (PPG), IQVNS can reduce the risk of electromagnetic interference stems from a PPG. In addition, we can avoid ground loop problems because the digital ground and the analog ground are isolated at VM.
IQVNS chips were fabricated using the AIST standard II process in which four Nb wiring layers and Nb/AlOx/Nb JJs with a critical current density of 2.5 kA/cm² are available. The functions of the fabricated chips were preliminary tested at low speed for selecting working chips.
We conducted JNT spectra measurements of a sense resistor with the IQVNS chip. The sense resistor of 99.9039 Ohm was at 273.16 K in a triple point of water cell. The IQVNS chip was clocked at 16384 (= 2¹⁴) MHz so as to obtain the power spectrum density as close as that of the sense resistor. Output voltages of the sense resistor and IQVNS were measured with 2 independent channels each of which was composed of a low noise amplifier, a low pass filter and a digitizer typically for 12 hours. The Boltzmann constant obtained by fitting the ratio of cross power spectra of the resistor and IQVNS agreed with the current CODATA value of 1.3806488 J/K within 130 ppm.

This work was supported by JSPS KAKENHI Grant No. 25289126 and No. 22246013.

We demonstrate programmable single-flux-quantum (SFQ) circuits using superconducting phase shift elements (PSEs) for constructing field programmable gate array (FPGA), which is getting a lot of attention from high performance computing application in recent years. The PSEs are achieved by magnetizing ferromagnetic patterns located in vicinity of superconducting loop. The programmable SFQ circuits are configured by adjusting strength or direction of magnetization in the patterns. We introduced this PSEs to SFQ AND gate as an instance of programmable SFQ circuits. We use a Pd_0.89Ni_0.11 alloy as ferromagnetic patterns and apply ±2190 A/m of magnetic field during circuit cooling process to magnetize the patterns. When the ferromagnetic patterns were magnetized as the specific direction and the opposite direction, the cell behaved as an AND gate and an OR gate, respectively. The normalized bias current margins are from 65% to 129% and from 89% to 106% for designed values in an AND function and an OR function, respectively. By optimizing the circuit parameters sufficiently, wider bias margins for an OR function will be obtained. We have tested other programmable SFQ cells such as a switch cell working like a non-destructive readout cell.
Based on the above-mentioned programmable gates, we can make up an FPGA. This FPGA has much potential to operate at several tens of GHz, which is about 100 times higher than present semiconductor FPGAs. Based on rough estimation, our FPGAs can be made up of half number of Josephson junctions compared to the previous SFQ FPGA [1]. If we introduce a multi-layer process like the AIST advanced process 2, the integration density is increased with a factor of more than 10.

[1] C. J. Fourie et. al., IEEE Trans. Appl. Supercond., Vol. 17, No. 2, pp. 538-541, JUNE (2007)

The circuits were partially fabricated in CRAVITY of National Institute of Advanced Industrial Science and Technology (AIST). This work is partly supported by ALCA-JST project entitled “Superconductor Electronic System Combined with Optics and Spintronics” and JSPS KAKENHI Grant Numbers 26420306, and 26220904.